FIG. 5 is an exemplary prior art device for generating a compensation signal for a power converter. In the example shown, the compensation signal is for a power factor correction (PFC) converter. A PFC converter causes a power converter to appear as a resistive load to the network supplying power to the power converter. By having the conversion device appear as a resistive load, the power required from the network versus the power generated is optimized and thus the system is more efficient and draws less current than if the power converter presented a low-power-factor load to the network. Prior art PFC regulation loops generate a slow (typically 10 Hz-20 Hz) compensation signal for the PFC converter to prevent compensation of second harmonic ripple (e.g. 100 Hz or 120 Hz) on the output bus. Compensation of the second harmonic ripple reduces the power factor of the PFC converter, so prior art PFC regulation loops circumvent this problem by slowing down the compensation loop to the point of ignoring 100 Hz or 120 Hz ripple on the bus.
FIG. 5 illustrates a prior art circuit 500 for generating a compensation signal 536 for a PFC converter 540. A bus voltage 542 is provided to a voltage divider 520, 520′ generating a scaled-bus voltage 521. The scaled-bus voltage 521 is input into an inverting input 531 of an error amplifier 533. A reference voltage source 534 provides a reference voltage to the non-inverting input 532 of the error amplifier 533. The reference voltage source 534 is typically a constant value scaled for a desired bus voltage 542. A filter compensation network 535 response time of 100 ms is typical to sufficiently remove the second harmonic ripple from the scaled-bus voltage 521 and produces an error reference signal 536 for the PFC converter controller 540.
Removal of a 100 Hz/120 Hz line ripple from the compensation signal 536 input to the PFC converter controller 540 prevents the PFC converter 541 from responding to the harmonic line ripple on the scaled-voltage bus 521. While the slow loop response allows filtering out of substantially all of the line-frequency ripple from the reference bus signal, the prior art design is not good at limiting transient voltage excursions caused upon application of a large load transient to a PFC converter 541. FIG. 6 illustrates various waveforms for a conventional prior art PFC converter system subject to a large load transient. Waveform 6A illustrates a curve of a load current as a function of time that incorporates a step in output load. The load current waveform 6A corresponds to a constant power load that is stepped up at time 400 ms and stepped down at time 600 ms. The ripple in the load current is a direct result of the variations in bus voltage and the fact that the load operates at constant power. Since PFC converters are usually connected to a second-stage converter which is a DC-to-DC converter, and the DC-to-DC converter acts as a constant power load, the curves shown in FIG. 6 correspond to a typical design situation.
The waveform 6B is a curve of AC input current into the conventional prior art PFC converter. The envelope of the AC input current rises between 400 ms and around 450 ms. After removal of the AC load at 600 ms, the AC input current drops back to pre-load levels after approximately 50 ms.
The waveform 6C is a curve of the PFC output bus voltage coupled to a conventional prior art PFC converter. At time 400 ms, at the application of the increased load, the bus voltage drops by about 50 volts between time 400 ms and 430 ms. This voltage drop can result in the undesirable side effect of causing the conventional prior art PFC convertor to drop out. The bus voltage recovers with some overshoot as shown around time 500 ms. After the increased bus load is removed (t=600 ms), the bus-voltage overshoots by around 30 volts between the time of 600 ms and 630 ms. The bus voltage is shown recovering back to the previous value at about 700 ms. Further, the negative-going voltage excursions (FIG. 6, curve 6C, 400-460 ms) causes the second-stage converter to operate over a larger voltage range, thus reducing the holdup time of the power supply immediately following a load transient as well as increasing the converter cost and lowering the overall converter efficiency. To limit the effect of the large voltage transients, large electrolytic capacitors are placed on the output of the PFC stage resulting in an increase in the cost and size for the PFC converter.
The bus-voltage transients, resulting from the load transients can cause the over-voltage protection to temporarily shut down the power supply. Another result of the uncontrolled transients, due to the slow compensated error signal response (6D in FIG. 6), is for electronic devices requiring larger voltage operating ranges in the second-stage converter (power supply).
Waveform 6D illustrates a compensation signal (536 in FIG. 5) of a prior art system configured to generate a compensation signal for a PFC converter. Because of the slow response time of the compensated error signal 536, the PFC converter 540 cannot quickly respond to the load transients (FIG. 6, curve 6A), due to the need to not respond to the line-voltage second harmonic. The compensation signal is clearly shown in FIG. 6, curve 6D. The response time of about 60 ms is required to respond to the load transient.
As a result, prior-art PFC converter designs have a number of design drawbacks. First, higher voltage rated semiconductors are required because of the voltage transients and thus the PFC converter incurs a higher manufacturing cost. Second, the second-stage converter requires larger transformers to handle the higher voltage range and thus impacts the PFC converter with lower efficiency and higher cost. Additionally, hold-up times following load transients are reduced thus causing performance issues. System design options are also limited because unregulated converter stages cannot be used in tandem with a PFC stage and thus limiting potential increased performance and cost savings.
Grid-tied inverters are another example of power converters that must regulate a DC bus while ignoring voltage variations on the bus that contain the second harmonic of the grid frequency. Grid-tied inverters, such as some photovoltaic inverters, have the same control and compensation issue as PFC converters. FIG. 9 shows a schematic representation of a typical grid-tied inverter 900. The photovoltaic array 920 or other source of power charges a high-voltage bulk capacitor 940 through a DC-to-DC converter 910 at a constant rate which is dependent on the currently available power (e.g. as a function of the level of light in the case of a photovoltaic inverter). The full-bridge inverter formed by switches (Q9-Q12) 951-954 and inductor (L6) 955 then produces a nearly sinusoidal current in phase with the grid voltage. As a result of the DC input power but sinusoidal output current, the voltage across bulk capacitor C3 contains a significant amount of second harmonic (e.g. 100/120 Hz) ripple. The inverter must adjust the amplitude of sinusoidal current that it pushes into the grid in order to regulate the voltage across bulk capacitor C3 940 to a desired level. The control loop to accomplish this regulation has exactly the same issues that have already been described for generating a PFC compensation signal.
What is needed is a circuit that produces a compensation signal representative of the bus voltage or that is substantially free of 100/120 Hz ripple but has a fast response to transients on the PFC converter (or grid-tied inverter) bus voltage.